1. Field of the Invention
Example embodiments of the present invention relate to a display driver circuit for a flat display panel and a display driving method using the same. More particularly, example embodiments of the present invention relate to a display driver circuit, a current sample/hold circuit, and a display driving method using the display driver circuit.
2. Description of the Related Art
A liquid crystal display (LCD) and a plasma display panel (PDP) are the two most common type of flat panel displays. Recently, an organic light emitting diode (OLED) display, which features higher contrast and/or quicker response time, is a type of display that has gain increased attention.
In order to implement a display driver circuit capable of supporting higher definition, a number of bits for a gray level should be increased. Accordingly, each of channels in the display driver circuit should process more data; however, the number of channels may increase as a size of a display panel increases.
A conventional display driver circuit, which may include a digital-to-analog converter (DAC) corresponding to each one of the channels, may be limited in its function as the number of the gray-scale bits and the number of the channels increases. Therefore, a display driver circuit capable of supporting an increased number of gray-scale bits and increased number of channels may be required.
FIG. 1 is a block diagram illustrating a conventional display driver circuit 100.
Referring to FIG. 1, the conventional display driver circuit 100 may include a shift register 110, a data interface circuit 120, a data latch circuit 130, a reference bias circuit 140, and/or an output circuit 150.
The shift register 110 may receive a clock signal CLK and output a shifted clock signal. The data interface circuit 120 may receive and process display data. The data latch circuit 130 may receive output signals from the data interface circuit 120 in response to the shifted clock signal output from the shift register 110, and output the display data to each of a plurality of channels in response to a latch enable signal LE. The reference bias circuit 140 may provide a reference value. The output circuit 150 may receive the output signals from the data latch circuit 130, convert the received output signals to analog output signals, and output the analog output signals to each of the plurality of channels.
In further detail, the shift register 110 may receive the clock signal CLK to shift the clock signal CLK to a left direction in response to a left input start pulse or shift the clock signal CLK to a right direction in response to a right input start pulse; the shift register 110 may store the shifted clock signal and output the shifted clock signal.
The data interface circuit 120 may receive and process the received display data corresponding to each of the plurality of channels, and output the processed display data to the data latch circuit 130.
The data latch circuit 130 may sample/hold output signals received from the data interface circuit 120 based on the shifted clock signal of the shift register 110. When the data latch circuit 130 receives all of the output signals of the data interface circuit 120, the data latch circuit 130 may output the sampled/held output signals to each of the plurality of channels based on the latch enable signal LE.
The output circuit 150 may receive the output signals of the data latch circuit 130. Each of a plurality of digital-to-analog converters (DAC) 152 included in the output circuit 150 may convert the corresponding output signals of the data latch circuit 130 to analog output signals, and output the analog output signals to the plurality of a plurality of channels via each of channel output circuits 154 also included in the output circuit 150.
FIG. 2 is a timing diagram to explain operations of the display driver circuit 100 shown in FIG. 1.
Referring to FIG. 2, when shift clocks CLK 1 through CLK Q corresponding to the number of channels N are turned on, a latch enable signal LE is activated on and output signals are output to all of a plurality of channels OUT 1 through OUT N.
If a size of a display panel becomes larger, the number of channels increases, and the number of DACs included in each of the channels also increases, and a chip size of the display driver circuit 100 also increases.
In addition, in order to implement high definition, a gray level may increase; thus, the number of processing bits of the DAC may also increase. As a result, a chip size of the DAC included in each of the channels may also increase, and the chip size of the display driver circuit 100 increases. If a display panel supporting a large scale panel and high definition is implemented using the conventional display driver circuit 100 shown in FIG. 1, a size of the display driver circuit 100 may be relatively large.